In recent years, progressive research and development has been conducted on nonvolatile memory devices which includes memory cells having variable resistance memory elements. A variable resistance memory element is an element which has a property where the resistance value reversibly changes according to an electrical signal, and which enables data corresponding to the resistance value to be written in a nonvolatile manner. Examples of the variable resistance memory element include a resistance random access memory (ReRAM) which is based on changes in electric resistance value caused due to oxidation-reduction reaction, a magnetoresistive random access memory (MRAM) which is based on changes in magnetroresistance, and a phase change random access memory (PCRAM) which is based on changes in electric resistance value caused due to phase change.
One example of a known nonvolatile memory device which includes the variable resistance memory elements is a so-called 1T1R type nonvolatile memory device in which a metal oxide semiconductor (MOS) transistor and a variable resistance memory element are connected in series at respective crosspoints of a bit line, a word line, and a source line that are orthogonally arranged. Another example is a so-called crosspoint type nonvolatile memory device in which a diode element and a variable resistance memory element are connected in series at respective crosspoints of a bit line and a word line that are orthogonally arranged in a similar manner.
For reading data from a memory device, a reference cell method (also referred to as a dummy cell method) is commonly used. In the method, reference cells (also referred to as dummy cells) are formed, each of which has an intermediate state of written information corresponding to the stored data “1” and data “0”, and information read from each memory cell is compared with the intermediate state to determine whether the read information is data “1” or data “0”. In the case of the nonvolatile memory device which includes the variable resistance memory elements, reference cells are formed, each of which has a resistance value of an intermediate state between a high resistance state and a low resistance state.
Patent Literature 1 discloses a configuration of a memory circuit of an MRAM with reduced number of reference cells.
FIG. 18 illustrates a circuit configuration of an MRAM device where a first memory cell array 1001 and a second memory cell array 1002, each of which has MRAM elements, are arranged horizontally with a sense amplifier 1005 therebetween. In addition, a first reference cell array 1003 is arranged adjacent to the first memory cell array 1001, and a second reference cell array 1004 is arranged adjacent to the second memory cell array 1002. When a memory cell MC included in the first memory cell array 1001 is selected for reading, a reference cell RC included in the second reference cell array 1004 is selected and the resistance values of the selected cells are compared by the sense amplifier 1005. When a memory cell MC included in the second memory cell array 1002 is selected for reading, a reference cell RC included in the first reference cell array 1003 is selected and the resistance values of the selected cells are compared by the sense amplifier 1005.
Each reference cell RC includes a fixed resistance element having a resistance value (reference value) between a low resistance state and a high resistance state of the memory cell MC. More specifically, the reference cell RC is formed by the process structure same as that of the memory cell MC, and has a fixed resistance value adjusted to a desired value by fixing the magnetization direction, and further changing the area of the ferromagnetic layer. Patent Literature 1 discloses a configuration where, for example, only a top 1-bit RCL 1 is used in the reference cell array 1003, and, for example, only a top 1-bit RCR 1 is used in the reference cell array 1004, thereby reducing the number of reference cells.
Patent Literature 2 discloses a crosspoint type ReRAM configuration including reference cells that can be trimmed.
FIG. 19 is a diagram of a basic configuration of a ReRAM device where a read operation is performed by comparing, using a sense amplifier 1012, a current flowing in a memory cell MC which is included in a memory cell array 1010 and in which a variable resistance element VR and a diode D1 are connected in series, with a current flowing in a reference cell block 1011 which has the same configuration as the memory cell MC. Here, the reference cell RCs in the reference cell block 1011 have the same cell configuration as the memory cells in the memory cell array 1010. The variable resistance element VRs in the reference cell RCs are set to the highest resistance state of all of the cells, that is, to the lowest memory cell current state. The variable resistance element VRs are connected in parallel. The number of reference cell RCs that are connected in parallel is trimmed to optimize the reference current value for reading data of the memory cell array 1010.